Makefile Variable Assignment

If these were single colons, an warning would be printed and only the second set of commands would run.4.12 Example requires: blah.c Generating prereqs automatically This makes one small makefile per source file Notes: 1) , with escaping.

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Although it is easy to think of variables as traditional programming language variables, there is a distinction between a macro “variable” and a “traditional” variable.

A macro variable is expanded “in place” to yield a text string that may then be expanded further.

# Adding PHONY to a target will prevent make from confusing the phony target with a file name.

# In this example, if clean is created, make clean will still be run.

5.6 The export directive takes a variable and makes it accessible to sub-make commands.

In this example, “cooly” is exported such that the makefile in subdir can use it. Use the special $(MAKE) instead of “make” because it will pass the make flags for you and won’t itself be affected by them.The first language describes dependency graphs consisting of targets and prerequisites.(This language was covered in Chapter 2.) The second language is a macro language for performing textual substitution.It’s a good idea to always use this, even though make does not for historical reasons.Add “-k” when running make to continue running even in the face of errors.Other macro languages you may be familiar with are the C preprocessor, allows you to define a shorthand term for a longer sequence of characters and use the shorthand in your program.The macro processor will recognize your shorthand terms and replace them with their expanded form.# PHONY is great to use, but I'll skip it in the rest of the examples for simplicity.# Implicit command of: "cc -c blah.c -o blah.o" # Note: 1) Do not put a comment inside of the blah.o rule; the implicit rule will not run!This distinction will become more clear as we proceed.A variable name can contain almost any characters including most punctuation.


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